This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-330619, Oct. 30, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a ferroelectric memory and a manufacturing method thereof, and more specifically to a memory having a structure in which a ferroelectric capacitor is disposed above a transistor, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, ferroelectric memories, which are non-volatile memories utilizing a ferroelectric thin film, have been progressively developed. Ferroelectric memories have a basic structure in that an insulating film used in the capacitor section of a DRAM is replaced with a ferroelectric film. Ferroelectric memories have the following characteristics and are expected to be memories of the next generation.
(1) It is possible to perform the writing and erasing at high speed. Where small memory cells are used, a writing time of 100 ns or less can be realized, as in DRAMs.
(2) It is possible to perform the rewriting many times. Where some schemes are put for ferroelectric materials (PZT, SBT, etc.), and electrode materials (Pt, IrOx, RuOx, SrRuO3, etc.), the number of rewrites can be 1012 or more.
(3) It is possible to realize high density and high degree of integration, as high as DRAMs in principle.
(4) It is possible to set the writing voltage used therein at about 2V, thereby reducing the power consumption.
(5) It is possible to perform a bit-rewriting and random access.
Because of these advantages, it has been realized or examined to apply the ferroelectric memories to many fields and directions. Furthermore, there is another future target of using the ferroelectric memories in place of DRAMs, SRAMs, or EEPROMs, by making the ferroelectric memories with high degree of integration and high capacity.
Ferroelectrics have a property of spontaneous polarization, whose direction can be reversed by electric fields. The spontaneous polarization has polarization values even when no electric field is applied (residual polarization), wherein the values (the direction of polarization) depend on a state before the electric field becomes zero. Depending on the direction of the electric field, an electrical charge of + (plus) or xe2x88x92 (minus) can be induced on the crystal surfaces, to correspond to xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d of memory elements. The ferroelectric memories can employ a structure of 1T/1C (one transistor/one capacitor) as in DRAMs, but they employ a structure of 2T/2C to ensure reliability under the current state of affairs.
As one of the types of these ferroelectric memories, there is a ladder type of structure, in which a transistor and a capacitor are connected in parallel, and a plurality of such combinations are connected in series. This type is advantageous in that the cell occupation area is small, because bit line plugs do not have to be led out from all cells.
However, even in ferroelectric memories having the ladder structure, it is not so easy to make them downsized and more highly integrated due to difficulties in working processes and fluctuations in properties. A three-dimensional arrangement of capacitors, which may be a technique of increasing capacity, is also thought to be more difficult because of the reasons described above, and other difficulties in working processes.
Specifically, for example, when electrode materials and ferroelectric materials are worked by RIE (Reactive Ion Etching), a conversion error, such as a CD (Critical Dimension) gain, is inevitable in the working process of capacitors, in addition to difficulties in the working process. The conversion error is necessary to prevent leakage current from increasing due to residues produced when electrode materials, such as Pt, is worked. Furthermore, even if a three-dimensional arrangement is adopted, a sufficient capacitor area is not necessarily secured, thereby hardly providing a sufficient quantity of electric charges for polarization.
With conventional techniques, it is unavoidable to employ very complicated processes, in order to solve these problems. Consequently, downsizing of memory cells by three-dimensional arrangements of capacitors has not been advanced sufficiently to obtain advantages for high degree of integration.
It is therefore demanded to develop a structure of ferroelectric memory and a method of manufacturing the same, which reduce the conversion error and fluctuation of patterns due to lithograph or downsize-working, and thus improve downsizing, degree of integration, and reliability.
According to a first aspect of the present invention, there is provided a ferroelectric memory including a transistor and a capacitor disposed on a semiconductor wafer, the memory comprising:
a first plug connected to one of source/drain regions of the transistor, and extending to a position above the transistor;
a second plug connected to the other of source/drain regions of the transistor and extending to a position above the transistor;
a first capacitor electrode connected to the first plug and located at a position above the transistor, the first capacitor electrode including first and second capacitor faces on the second plug side and a side reverse thereto, respectively;
a ferroelectric film disposed on the first capacitor face of the first capacitor electrode; and
a second capacitor electrode connected to the second plug and located at a position above the transistor, the second capacitor electrode being disposed on the first capacitor face of the first capacitor electrode through the ferroelectric film.
According to a second aspect of the present invention, there is provided a ferroelectric memory comprising:
a semiconductor substrate;
first, second, and third source/drain regions formed in a surface of the substrate, the first source/drain region being interposed between the second and third source/drain regions;
first and second gate electrodes facing, through a gate insulating film, a first channel region between the first and second source/drain regions, and a second channel region between the first and third source/drain regions, respectively;
an inter-level insulating film covering the first, second, and third source/drain regions;
first, second, and third plugs penetrating the inter-level insulating film, and electrically connected to the first, second, and third source/drain regions, respectively;
a first capacitor electrode disposed above the first source/drain region, and electrically connected to the first source/drain region via the first plug;
first and second capacitor insulating films each comprising a ferroelectric film, formed on side surfaces of the first capacitor electrode facing the second and third source/drain regions; and
second and third capacitor electrodes disposed above the second and third source/drain regions, and electrically connected to the second and third source/drain regions via the second and third plugs, respectively, the second and third capacitor electrodes facing the first capacitor electrode through the first and second capacitor insulating films, respectively.
According to a third aspect of the present invention, there is provided a method of manufacturing a ferroelectric memory including a transistor and a capacitor disposed on a semiconductor wafer, the method comprising:
forming a first plug connected to one of source/drain regions of the transistor, and extending to a position above the transistor;
forming a second plug connected to the other of source/drain regions of the transistor and extending to a position above the transistor;
forming a first capacitor electrode connected to the first plug and located at a position above the transistor, the first capacitor electrode including first and second capacitor faces on the second plug side and a side reverse thereto, respectively;
forming a ferroelectric film disposed on the first capacitor face of the first capacitor electrode; and
forming a second capacitor electrode connected to the second plug and located at a position above the transistor, the second capacitor electrode being disposed on the first capacitor face of the first capacitor electrode through the ferroelectric film.